This invention relates to an access load distribution for a computer system.
Examples of a background art include, as disclosed in JP 2000-330924 A, a technique in which a plurality of accessible paths are provided between a storage system and a computer, and accesses made by the computer are distributed across those paths, thereby improving a system performance. According to such a technique for a load balance, access (I/O) loads are distributed across the plurality of paths, thereby preventing the performance from decreasing due to accesses concentrated on a specific path. In addition, when a failure occurs in one path, the accesses are allocated to another normal path so as to allow continuous accesses.
An alternative technique is proposed in, for example, JP 2002-182978 A, in which a cache memory mounted to a storage system is used for improving a system performance. Examples of the technique include a cache pre-reading technique in which, in addition to data of a block relating to a read request, data of the subsequent block is also read out and stored in the cache memory, thereby improving an access performance.